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1-mbit (64k x 16) static ram cy7c1021cv33 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05132 rev. *g revised november 6, 2006 features ? temperature ranges ? commercial: 0c to 70c ? industrial: ?40c to 85c ? automotive-a: ?40c to 85c ? automotive-e: ?40c to 125c ? pin- and function-compatible with cy7c1021bv33 ?high speed ?t aa = 8 ns (commercial & industrial) ?t aa = 12 ns (automotive) ? cmos for optimum speed/power ? low active power: 345 mw (max.) ? automatic power-down when deselected ? independent control of upper and lower bits ? available in pb-free and non pb-free 44-pin 400-mil soj 44-pin tsop ii and 48-ball fbga packages functional description [1] the cy7c1021cv33 is a high-performance cmos static ram organized as 65,536 words by 16 bits. this device has an automatic power-down featur e that significantly reduces power consumption when deselected. writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 1 through i/o 8 ), is written into the location specified on the address pins (a 0 through a 15 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 9 through i/o 16 ) is written into the location specified on the address pins (a 0 through a 15 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins will appear on i/o 1 to i/o 8 . if byte high enable (bhe ) is low, then data from memory will appear on i/o 9 to i/o 16 . see the truth table at the end of this data sheet for a complete description of read and write modes. the input/output pins (i/o 1 through i/o 16 ) are placed in a high-impedance state when the device is deselected (ce high), the outputs are disabled (oe high), the bhe and ble are disabled (bhe , ble high), or during a write operation (ce low, and we low). the cy7c1021cv33 is available in 44-pin 400-mil wide soj, 44-pin tsop ii and 48-ball fbga packages. note: 1. for best-practice recommendations, please refer to the cypr ess application note ?system design guidelines? on http://www.cypr ess.com. logic block diagram 64k x 16 ram array i/o 1 ?i/o 8 row decoder a 7 a 6 a 5 a 4 a 3 a 0 column decoder a 9 a 10 a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe a 2 a 1 i/o 9 ?i/o 16 ce we ble bhe a 8 [+] feedback [+] feedback
cy7c1021cv33 document #: 38-05132 rev. *g page 2 of 13 selection guide -8 -10 -12 -15 unit maximum access time 8 10 12 15 ns maximum operating current comm?l/ind?l 95 90 85 80 ma automotive-a 80 ma automotive-e 90 ma maximum cmos standby current comm?l/ind?l 5 5 5 5 ma automotive-a 5 ma automotive-e 10 ma pin configurations [2] we v cc a 11 a 10 nc a 6 a 0 a 3 ce i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe v ss a 7 i/o 0 bhe nc a 2 a 1 ble v cc i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 nc nc nc 3 2 6 5 4 1 d e b a c f g h nc nc 1 2 3 4 5 6 7 8 9 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 a 5 18 17 20 19 27 28 25 26 22 21 23 24 48-ball fbga soj/tsop ii top view top view a 6 a 7 a 4 a 3 a 2 a 1 a 0 a 14 a 15 a 8 a 9 a 10 a 11 a 12 a 13 nc nc oe bhe ble ce we i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 i/o 16 v cc v cc v ss v ss nc 10 note: 2. nc pins are not connected on the die. [+] feedback [+] feedback
cy7c1021cv33 document #: 38-05132 rev. *g page 3 of 13 pin definitions pin name soj, tsop pin number bga pin number i/o type description a 0 ?a 15 1?5, 18?21, 24?27, 42?44 a3, a4, a5, b3, b4, c3, c4, d4, h2, h3, h4, h5, g3, g4, f3, f4 input address inputs used to select one of the address locations. i/o 0 ?i/o 15 [3] 7?10, 13?16, 29?32, 35?38 b6, c6, c5, d5, e5, f5, f6, g6, b1, c1, c2, d2, e2, f2, f1, g1 input/output bidirectional data i/o lines . used as input or output lines depending on operation. nc 22, 23, 28 a6, d3, e3, e4, g2, h1, h6 no connect no connects . not connected to the die. we 17 g5 input/control write enable input, active low . when selected low, a write is conducted. when deselected high, a read is conducted. ce 6 b5 input/control chip enable input, active low . when low, selects the chip. when high, deselects the chip. bhe , ble 40, 39 b2, a1 input/control byte write select inputs, active low . bhe controls i/o 16 ?i/o 9 , ble controls i/o 8 ?i/o 1 . oe 41 a2 input/control output enable, active low . controls the direction of the i/o pins. when low, the i/o pins are allowed to behave as outputs. when deasserted high, i/o pins are tri-st ated, and act as input data pins. v ss 12,34 d1, e6 ground ground for the device . should be connected to ground of the system. v cc 11,33 d6, e1 power supply power supply inputs to the device. note: 3. i/o 1 ?i/o 16 for soj/tsop and i/o 0 ?i/o 15 for bga packages. [+] feedback [+] feedback
cy7c1021cv33 document #: 38-05132 rev. *g page 4 of 13 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ?65 c to +150 c ambient temperature with power applied............................................. ?55 c to +125 c supply voltage on v cc relative to gnd [4] .... ?0.5v to +4.6v dc voltage applied to outputs in high-z state [4] ......................................?0.5v to v cc +0.5v dc input voltage [4] ...................................?0.5v to v cc +0.5v current into outputs (low) .... .....................................20 ma static discharge voltage......... .............. .............. ....... >2001v (per mil-std-883, method 3015) latch-up current...................................................... >200 ma operating range range ambient temperature (t a )v cc commercial 0 c to +70 c 3.3v 10% industrial ?40 c to +85 c automotive-a ?40 c to +85 c automotive -e ?40 c to +125 c electrical characteristics over the operating range parameter description test conditions -8 -10 -12 -15 unit min. max. min. max. min. max. min. max. v oh output high voltage v cc = min., i oh = ?4.0 ma 2.4 2.4 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 0.4 0.4 v v ih input high voltage 2.0 v cc + 0.3 2.0 v cc + 0.3 2.0 v cc + 0.3 2.0 v cc + 0.3 v v il input low voltage [4] ?0.3 0.8 ? 0.3 0.8 ?0.3 0.8 ?0.3 0.8 v i ix input leakage current gnd < v i < v cc com?l/ind?l ? 1 + 1 ? 1+1?1+1?1+1 a auto-a ?1 +1 auto-e ?12 +12 i oz output leakage current gnd < v i < v cc , output disabled com?l/ind?l ? 1 + 1 ? 1+1?1+1?1+1 a auto-a ?1 +1 auto-e ?12 +12 i cc v cc operating supply current v cc = max., i out = 0 ma, f = f max = 1/t rc com?l/ind?l 95 90 85 80 ma auto-a 80 ma auto-e 90 i sb1 automatic ce power-down current ?ttl inputs max. v cc , ce > v ih v in > v ih or v in < v il , f = f max com?l/ind?l 15 15 15 15 ma auto-a 15 auto-e 20 i sb2 automatic ce power-down current ?cmos inputs max. v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f = 0 com?l/ind?l 5 5 5 5 ma auto-a 5 auto-e 10 note: 4. v il (min.) = ?2.0v and v ih (max) = v cc + 0.5v for pulse durations of less than 20 ns. [+] feedback [+] feedback
cy7c1021cv33 document #: 38-05132 rev. *g page 5 of 13 ac test loads and waveforms [6] notes: 5. tested initially and after any design or proc ess changes that may affect these parameters. 6. ac characteristics (except high-z) for all 8-ns parts are test ed using the load conditions shown in figure (a). all other spe eds are tested using the thevenin load shown in figure (b). high-z characteristics are tested fo r all speeds using the test load shown in figure (d). capacitance [5] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 8 pf c out output capacitance 8 pf thermal resistance [5] parameter description test conditions soj tsop ii fbga unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51 65.06 76.92 95.32 c/w jc thermal resistance (junction to case) 34.21 15.86 10.68 c/w 90% 10% 3.0v gnd 90% 10% all input pulses 3.3v output 30 pf* * capacitive load consists of all components of the test environment (b) r 317 ? r2 351 ? rise time: 1 v/ns fall time: 1 v/ns 30 pf* output z = 50 ? 50 ? 1.5v (c) (a) 3.3v output 5 pf (d) r 317 ? r2 351 ? 8-ns devices: 10-, 12-, 15-ns devices: high-z characteristics: [+] feedback [+] feedback
cy7c1021cv33 document #: 38-05132 rev. *g page 6 of 13 switching characteristics over the operating range [7] parameter description -8 -10 -12 -15 unit min. max. min. max. min. max. min. max. read cycle t power [8] v cc (typical) to the first access 100 100 100 100 s t rc read cycle time 8 10 12 15 ns t aa address to data valid 8 10 12 15 ns t oha data hold from address change 3 3 3 3 ns t ace ce low to data valid 8 10 12 15 ns t doe oe low to data valid 5 5 6 7 ns t lzoe oe low to low-z [9] 0000ns t hzoe oe high to high-z [9, 10] 4567ns t lzce ce low to low-z [9] 3333ns t hzce ce high to high-z [9, 10] 4567ns t pu [11] ce low to power-up 0 0 0 0 ns t pd [11] ce high to power-down 8 10 12 15 ns t dbe byte enable to data valid 5 5 6 7 ns t lzbe byte enable to low-z 0 0 0 0 ns t hzbe byte disable to high-z 4 5 6 7 ns write cycle [12] t wc write cycle time 8 10 12 15 ns t sce ce low to write end 7 8 9 10 ns t aw address set-up to write end 7 8 9 10 ns t ha address hold from write end 0 0 0 0 ns t sa address set-up to write start 0 0 0 0 ns t pwe we pulse width 6 7 8 10 ns t sd data set-up to write end 5 5 6 8 ns t hd data hold from write end 0 0 0 0 ns t lzwe we high to low-z [9] 3333ns t hzwe we low to high-z [9, 10] 4567ns t bw byte enable to end of write 6 7 8 9 ns notes: 7. test conditions assume signal transition ti me of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v. 8. t power gives the minimum amount of time that the power supply should be at typical v cc values until the first memory access is performed. 9. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 10. t hzoe , t hzbe , t hzce , and t hzwe are specified with a load c apacitance of 5 pf as in part (d) of ac te st loads. transition is measured 500 mv from steady-state voltage. 11. this parameter is guaranteed by design and is not tested. 12. the internal write time of the me mory is defined by the overlap of ce low, we low and bhe /ble low. ce , we and bhe /ble must be low to initiate a write, and the transition of these signals can terminate the writ e. the input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. [+] feedback [+] feedback
cy7c1021cv33 document #: 38-05132 rev. *g page 7 of 13 switching waveforms read cycle no. 1 (address transition controlled) [13, 14] read cycle no. 2 (oe controlled) [14, 15] notes: 13. device is continuously selected. oe , ce , bhe and/or ble = v il . 14. we is high for read cycle. 15. address valid prior to or coincident with ce transition low. previous data valid data valid rc t aa t oha t rc address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzbe t pd t dbe t lzbe t hzce high impedance i cc i sb oe ce address data out v cc supply bhe ,ble current [+] feedback [+] feedback
cy7c1021cv33 document #: 38-05132 rev. *g page 8 of 13 write cycle no. 1 (ce controlled) [16, 17] write cycle no. 2 (ble or bhe controlled) notes: 16. data i/o is high impedance if oe or bhe and/or ble = v ih . 17. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. switching waveforms (continued) t hd t sd t sce t sa t ha t aw t pwe t wc bw t data i/o address ce we bhe ,ble t hd t sd t bw t sa t ha t aw t pwe t wc t sce data i/o address bhe ,ble ce we [+] feedback [+] feedback
cy7c1021cv33 document #: 38-05132 rev. *g page 9 of 13 write cycle no. 3 (we controlled, low) truth table ce oe we ble bhe i/o 1 ?i/o 8 [3] i/o 9 ?i/o 16 [3] mode power h x x x x high-z high-z power-down standby (i sb ) l l h l l data out data out read ? all bits active (i cc ) l h data out high-z read ? lower bits only active (i cc ) h l high-z data out read ? upper bits only active (i cc ) l x l l l data in data in write ? all bits active (i cc ) l h data in high-z write ? lower bits only active (i cc ) h l high-z data in write ? upper bits only active (i cc ) l h h x x high-z high-z selected, outputs disabled active (i cc ) l x x h h high-z high-z selected, outputs disabled active (i cc ) switching waveforms (continued) t hd t sd t sce t ha t aw t pwe t wc t bw t sa t lzwe t hzwe data i/o address ce we bhe ,ble [+] feedback [+] feedback
cy7c1021cv33 document #: 38-05132 rev. *g page 10 of 13 ordering information speed (ns) ordering code package diagram package type operating range 8 cy7c1021cv33-8vxc 51-85082 44-pin (400-mil) molded soj (pb-free) commercial cy7c1021cv33-8zxc 44-pin tsop type ii (pb-free) CY7C1021CV33-8BAXC 51-85096 48-ball fbga (pb-free) 10 cy7c1021cv33-10vc 51-85082 44-pin (400-mil) molded soj commercial cy7c1021cv33-10vxc 44-pin (400-mil) molded soj (pb-free) cy7c1021cv33-10zxc 51-85087 44-pin tsop type ii (pb-free) cy7c1021cv33-10zi 44-pin tsop type ii industrial cy7c1021cv33-10zxi 44-pin tsop type ii (pb-free) cy7c1021cv33-10baxi 51-85096 48-ball fbga (pb-free) 12 cy7c1021cv33-12vc 51-85082 44-pin (400-mil) molded soj commercial cy7c1021cv33-12vxc 44-pin (400-mil) molded soj (pb-free) cy7c1021cv33-12vi 44-pin (400-mil) molded soj industrial cy7c1021cv33-12vxi 44-pin (400-mil) molded soj (pb-free) cy7c1021cv33-12zxc 51-85087 44-pin tsop type ii (pb-free) commercial cy7c1021cv33-12zxi 44-pin tsop type ii (pb-free) industrial cy7c1021cv33-12bai 51-85096 48-ball fbga industrial cy7c1021cv33-12baxi 48- ball fbga (pb-free) cy7c1021cv33-12zse 51-85087 44-pin tsop type ii automotive-e cy7c1021cv33-12zsxe 44-pin tsop type ii (pb-free) cy7c1021cv33-12ve 51-85082 44-pin (400-mil) molded soj cy7c1021cv33-12vxe 44-pin (400-mil) molded soj (pb-free) cy7c1021cv33-12bae 51-85096 48-ball fbga 15 cy7c1021cv33-15vxc 51-85082 44-pin (400-mil) molded soj (pb-free) commercial cy7c1021cv33-15zxc 51-85087 44-pin tsop type ii (pb-free) commercial cy7c1021cv33-15zi 44-pin tsop type ii industrial cy7c1021cv33-15zxi 44-pin tsop type ii (pb-free) cy7c1021cv33-15baxi 51-85096 48-ball fbga (pb-free) cy7c1021cv33-15zsxa 51-85087 44-pin tsop type ii (pb-free) automotive-a please contact local sales representative regarding availability of these parts [+] feedback [+] feedback
cy7c1021cv33 document #: 38-05132 rev. *g page 11 of 13 package diagrams 44-pin (400-mil) molded soj (51-85082) 51-85082-*b 44-pin thin small outline package type ii (51-85087) 51-85087-*a [+] feedback [+] feedback
cy7c1021cv33 document #: 38-05132 rev. *g page 12 of 13 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. all products and company names mentioned in this doc ument are the trademarks of their respective holders. package diagrams (continued) g f e d c b a 5 64321 pin 1 corner 5.25 3.75 0.75 0.75 ?0.300.05(48x) ?0.25 m c a b 0.15(4x) 0.210.05 1.20 max. seating plane 0.530.05 0.25 c 0.10 c h e h f g a b c d 6 5 12 3 4 pin 1 corner top view bottom view 7.000.10 7.000.10 a b ?0.05 m c (laser mark) b a c 7.000.10 7.000.10 1.875 2.625 0.36 48-ball fbga (7 x 7 x 1.2 mm) (51-85096) 51-85096-*f [+] feedback [+] feedback
cy7c1021cv33 document #: 38-05132 rev. *g page 13 of 13 document history page document title: cy7c1021cv33, 1-mbit (64k x 16) static ram document number: 38-05132 rev. ecn no. issue date orig. of change description of change ** 109472 12/06/01 hgk new data sheet *a 115044 05/08/02 hgk ram7 version c4k x 16 async remove ?preliminary? *b 115808 06/25/02 hgk i sb1 and i cc values changed *c 120413 10/31/02 dfp updated bga pin e4 to nc *d 238454 see ecn rkf 1) added automotive specs to data sheet 2) added pb-free devices in the ordering information *e 334398 see ecn syt added pb-free on page# 9 and 10 *f 493565 see ecn nxr added automotive-a operating range corrected typo in the pin definition table changed the description of i ix from input load current to input leakage current in dc electrical characteristics table removed i os parameter from dc electrical characteristics table updated the ordering information table *g 563963 see ecn vkn added t power spec in the ac switching characteristics table added footnote #8 [+] feedback [+] feedback

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